This invention relates in general to the field of electronics and more specifically to a method for measuring the lock time of a phase lock loop (PLL) circuit.
The lock time of a PLL circuit is typically measured using Automatic Test Equipment (ATE) that perform Fast Fourier Transforms (FFTs) on a small time window of a captured PLL output signal. The window is moved across the captured data waveform and the frequency is measured using the FFT. This prior art technique suffers from three main problems. First, the frequency resolution depends on the samples in the window. Therefore, in order to maintain good time resolution, the PLL output signal has to be captured at a very high speed to get enough samples in the small time window. Secondly, this method inherently suffers from spectral leakage in the FFT, which reduces the overall accuracy of the resulting measurement. And lastly, since FFTs have to be performed on a large number of windows, the overall test time is very long.
Given the problems mentioned above, some manufactures of radio frequency (RF) devices, such as synthesizers that use PLL circuits, do not measure PLL lock times for each RF device. Lock times for these integrated circuits (ICs) are typically characterized in the lab using test equipment such as Agilent""s 4352B, VCO/PLL Signal Analyzer or a Hewlett-Packard HP53310A, Modulation Domain Analyzer, on a small sample of the manufactured ICs. However, given that the PLL lock time is a very critical parameter in applications such as cellular radios and other applications where PLL lock times are critical, it important that PLL lock times be tested in production, in order to assure ICs meet their PLL lock time specifications. Thus, it would be beneficial in the art if a method were available that would allow for the measuring of PLL lock times accurately and in a short amount of time.